*********************************
There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
*********************************
Title: Exploration, Modeling, and Optimization of Advanced Interconnects: Solutions to Node Scaling Challenges
Committee:
Dr. Naeemi, Advisor
Dr. Lim, Co-Advisor
Dr. Davis, Chair
Dr. Mukhopadhyay
Abstract: The objective of the proposed research is to explore novel interconnect options and to develop an accurate modeling/technology-design co-optimization flow to evaluate BEOL improvements at the advanced nodes. The modeling framework includes the BEOL impact on circuit performance (inter-cell connections) as well as wire parasitics within standard cells and SRAM memory blocks (intra-cell connections) and their impact on full chip circuit performance. The preliminary research includes exploration of 3D IC design space with 3D clocktree methods and re-exploration of low power techniques in the context of 3D ICs as well as the modeling and benchmarking of different interconnects options. The proposed research aims to expand the interconnect modeling framework and provide a way to easily perform a wholistic analysis of different BEOL options on full chip power, performance, and area (PPA).
