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Title: Cryogenic CMOS circuits for High-Performance Digital Systems
Committee:
Dr. Arijit Raychowdhury (Advisor)
Dr. Suman Datta (Chair)
Dr. Sung-Kyu Lim
Abstract: The objective of the proposed research is to demonstrate voltage-temperature scalable CPU core with improved performance at cryogenic temperature. Cryogenic operation provides numerous advantages like steeper switching characteristics, improved carrier transport and lower interconnect resistivity to highlight a few. However, the threshold voltage (Vt) increase at cryogenic temperature is one of the limiting factors impeding system performance enhancement arising from these superior device characteristics. We deploy two circuit techniques to mitigate the impact of Vt increase (1) applying suitable body bias to decrease Vt (2) boost power supply voltage to create additional headroom. The approach includes threshold voltage monitoring circuit which is used in adaptive feedback closed loop to vary the body bias and/or supply voltage to the clock generating PLL and the core itself. Further, we benchmark this design against iso-IOFF placed-and-routed design databases.
