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There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
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Title: Dense Interconnection and Advanced Cooling Technologies for 2.5D and 3D Heterogeneous Integrated Circuits
Committee:
Dr. Muhannad Bakir, ECE, Chair, Advisor
Dr. Gary May, ECE, Co-Advisor
Dr. Albert Frazier, ECE
Dr. John Cressler, ECE
Dr. Tushar Krishna, ECE
Dr. Yogendra Joshi, ME
Abstract: The objective of the proposed research is to design and demonstrate advanced interconnection and thermal management solutions for 2.5D and 3D heterogeneous ICs. Modern compute workloads require hardware capabilities which cannot be provided by the ever-slowing transistor scaling. This has driven the recent surge towards heterogeneous integration, where advanced 2.5D and 3D ICs complement System-on-Chip (SoC) innovations to provide high performance, low cost, and more customizable System-in-Packages (SiPs). In this work, we investigate enabling technologies that can help address the interconnection and thermal management issues in SiP scaling. First, we discuss a new interconnect platform that uses mechanical self-alignment in conjunction with metal electroless deposition as a method to facilitate low temperature, low pressure, and high interconnect density inter-die bonding in heterogeneous 2.5D and 3D ICs. This method is a highly scalable alternative to the conventional solder-based interconnects but comes without the stringent requirements such as high temperature tolerance, high pressure process, extreme surface planarity and cleanliness, and very accurate initial alignment requirements of Cu-Cu direct bonding. Secondly, the compute and cooling efficiency benefits of silicon-integrated monolithic microfluidic cooling were investigated on a high-power functional CPU running real-world benchmarks. Next, the technology was scaled to 2.5D architectures and was evaluated on an Intel FPGA with five discrete dice. Finite volume simulations and measurement data were used to quantify the benefits in terms of managing higher aggregate package power, and minimizing the thermal coupling between closely spaced dice in 2.5D SiPs. Finally, the interconnection and thermal management co-design challenges were evaluated for a 3D stack with inter-layer microfluidic cooling. Fabrication optimizations for very high aspect ratio TSVs were developed and the thermal-electrical trade-offs for these vertical interconnects were analyzed using measurements and 3D-EM simulators.
