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There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
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Atlanta, GA | Posted: April 19, 2011
Congratulations to Qiao Chen and his Advisor, Rao Tummala, on winning the IEEE 2011 ECTC Travel Award for “Low-Cost, Panel-based Silicon Interposer with Fine- Pitch Through-Package-Vias” at the 61th IEEE Electronic Components and Technology Conference, which will be held in Lake Buena Vista, Florida this coming June. This honor is shared with coauthors Mr. Tapobrata Bandyopadhyay, Dr. Fuhan Liu, Dr. Venky Sundaram, Dr. Raghuram Pucha, Prof. Madhavan Swaminathan, Prof. Rao Tummala of Georgia Tech along with Mr. Yuya Suzuki of Zeon Corporation.
CMOS-based ICs are viewed as beginning to reach performance limits beyond 16 nm, and the industry focus, therefore, has begun to change to 3D IC stacking for shortest interconnection length using through-silicon-vias (TSVs). These 3D ICs, however, require 20-50 µm pitch off chip interconnections to package them, as opposed to the current 150 µm pitch for 2D ICs currently. Silicon interposers are being developed widely around the globe, as organic interposers reach their limits in I/Os, thermal dissipation, mechanical stress and warpage due to the large CTE mismatch between silicon devices and organic interposers. However, the current approach, based on 200-300 mm wafers may be too expensive for many consumer electronics applications. The paper presents, for the first time, a radically different panel-based polycrystalline silicon interposer with the potential to achieve highest I/Os at significantly lower cost.
Congratulations, Qiao!
