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Title: Near Memory Hardware Accelerators for Radio Frequency Signal Computation
Committee:
Dr. Mukhopadhyay, Advisor
Dr. Romberg, Chair
Dr. Krishna
Abstract: The objective of the proposed research is the design of hardware accelerators/control path in hardware accelerators for Radio Frequency signal computation based on Near Memory techniques. Radio Frequency (RF) applications like RF Machine learning and real-time RF environments (radar, electronic warfare) have constraints of high accuracy in data formats, high throughput and low latency. They require the design of application specific integrated circuits (ASICs) to simultaneously meet all the requirements. Processing-in-Memory (PIM) accelerators have shown promise for computation in traditional Machine learning applications involving dot product of matrices, but are restricted in data format and precision. First, this research focuses on extending the capability of In/Near Memory hardware accelerators to handle RF data with high precision. A fully digital processing-in-memory accelerator for Vector Matrix Multiplication with support for flexible precision, floating point and complex numbers is designed. The test-chip is fabricated in 65nm CMOS and demonstrates a measured compute efficiency of 34 GOPS/W/KB (normalized to memory size). The PIM accelerator enables in-memory radio frequency machine learning and signal processing computation. Further, the research aims to demonstrate an ASIC based distributed control architecture in a Near Memory hardware accelerator for a fully closed loop large scale real-time RF environment with high throughput, low end-to-end latency and high compute. A small scale prototype design is taped out in 28nm CMOS on a 6sq.mm. die for a 4 object system over an 8μs emulation range to verify functionality of the architecture and characterize power and frequency. The research seeks to extend the work to implementation of control path for an 8 object system over an emulation range of 50μs.
