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Title: Design and Optimization of Integrated Plasmonic Devices for High-Performance Computing
Committee:
Dr. Naeemi, Advisor
Dr. Davis, Chair
Dr. Cai
Abstract: The objective of the proposed research is to design a CMOS compatible integrated plasmonic computing network with optimized system-level performance, considering the trade-off among area, throughput, and energy requirement. Plasmonics, a synergy between photonics and electronics, has opened a wealth of prospects in ultrafast computing offering high throughput and dense integration capability. To realize plasmon-based computing, during the design process, it is crucial to consider the interaction among the connected components and trade-offs among different performance parameters. However, research in this area has mainly focused on the design or demonstration of individual device components in isolation, and there has not been any systemic and comprehensive research effort considering all the major aspects of a plasmonic computing system. The envisioned computing system will include plasmonic modulators to control the phase of the logic gate input, plasmonic logic gate for wave-computation, plasmon detector to convert the output of the logic gate to electrical domain, and a high-speed CMOS receiver circuit. We consider a plasmonic metal-insulator-metal (MIM) logic gate that can perform Boolean as well as non-Boolean functionalities like majority operation producing multiple output levels. We design a Ge-based asymmetric metal-semiconductor-metal (MSM) plasmonic detector and optimize it for detecting the output levels of the integrated majority gate. Through numerical analyses, the optimized detector is predicted to offer a low dark current of a few nA, responsivity of 0.32A/W, < 0.5fF of capacitance, and an intrinsic bandwidth of 250GHz at only 100mV of applied bias. From the integrated plasmonic logic-detector combination, we determine the maximum allowable input impedance of the CMOS receiver circuit for a target system bandwidth. We will integrate the phase modulators and receiver circuit to move towards the complete integrated system design. Apart from the majority gate, the plasmonic MIM waveguide (WG) has been extensively utilized to design and demonstrate plasmonic devices. These devices require coupling with the plasmon detector (MSM WG) to interface with the CMOS circuit. We provide a quantitative comparison of different couplers between plasmonic MIM and MSM waveguide and formulate a holistic performance metric to benchmark the coupling approaches. Finally, we identify a novel coupling scheme, namely perpendicular coupling, which is unparalleled in the conventional dielectric waveguiding, as the most attractive choice among all the couplers.
