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Title: Understanding the interfacial effects and defects in ferroelectric field effect transistors
Committee:
Dr. Khan, Advisor
Dr. Yu, Chair
Dr. Raychowdhhury
Dr. Datta
Abstract: The objective of this research is to design a front end FEFET with logic compatible write voltage, acceptable memory window and enhanced reliability for embedded memory applications. Despite having been discussed since 1960s, there are significant gaps in our fundamental understanding of the FEFET's behavior. Charge trapping or polarization screening in FEFETs has been suggested as the reason behind the weak electrostatic coupling that ultimately leads to lower than expected memory window in these devices. This proposed research will attempt to conduct experiments to understand the device physics of the FEFET. The intuition obtained from these experiments will help us update the FEFET's gate design for its integration in embedded platforms and advanced technology nodes. We will additionally employ different methods such as interfacial layer engineering via oxygen scavenging technique, gate metal engineering to move towards the optimal FEFET design. Combined electrical and structural analysis on the fabricated samples will provide significant insight into processes necessary to engineer the gate-stack of an FEFET and enhance its performance as a non-volatile memory element.
