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Title: Accelerating Deep Neural Network (DNN) Processing with Emerging-memory-technology-driven Architectures
Committee:
Dr. Yu, Advisor
Dr. Mukhopadhyay, Chair
Dr. Krishna
Abstract: The object of the proposed research is to design energy efficient DNN accelerators with emerging non-volatile memory technologies. To reduce the energy consuming off-chip DRAM access, compute-in-memory (CIM) paradigm using eNVM has been proposed recently. However, although CIM achieves good performance for DNN inference, the energy efficiency for DNN training is not satisfactory due to the high write energy of eNVM. To enable energy efficient training, CIM accelerator design using eNVM-based hybrid precision synapse is proposed. To support training on edge device, CIM accelerator design for incremental learning is proposed with an algorithm-hardware co-design approach. Network-expansion-based low precision training algorithm is adopted to effective support incremental learning. A hardware resources assignment protocol is devised for high throughput during partial training. As a plan for future research, to equip the accelerator with high density and low standby power on-chip buffer, I propose to operate ferroelectric RAM in both volatile and non-volatile modes. Architectural protocol and hardware design to support dual-mode operation will be further investigated. To design reconfigurable CIM accelerator with low area overhead, I propose to replace the conventional 1 SRAM + 1 NMOS switch with back-end-of-line (BEOL) Indium-Tungsten-Oxide (IWO) ferroelectric field effect transistor (FeFET) using monolithic 3D integration scheme. A reconfiguration algorithm to determine the connectivity between routing switches is to be devised to optimize the communication latency for different DNN models.
