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Title: Modeling and Simulation of FinFET SRAM Reliability Degraded by Various Wearout Mechanisms
Committee:
Dr. Linda Milor, ECE, Chair , Advisor
Dr. Azad Naeemi, ECE
Dr. Gregory Durgin, ECE
Dr. Benjamin Klein, ECE
Dr. Chenyun Pan, U Texas Arlington
Abstract: The objective of this dissertation is to develop frameworks for performance-reliability degradation of FinFET SRAM due to wearout mechanisms including Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Random Telegraph Noise (RTN), and Electromigration (EM). Since the first three mechanisms appear in front-end, while EM appears in back-end, the modeling and simulation methodologies designed for aging due to them are different. The frameworks target at providing advice to SRAM cache designers. The decision on parameter selection for a cache depends on the designer’s requirements on various factors, such as acceptable performance, reliability, aging, area, complexity of hardware implementation, etc. Our frameworks can be utilized to provide cache designers with some potential advice on parameter selection with regard to reliability and performance.
