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Title: Thermal, Power Delivery, and Signaling Considerations for Emerging Heterogeneous Integration Architectures and Devices
Committee:
Dr. Bakir, Advisor
Dr. Raychowdhury, Chair
Dr. Yu
Abstract: The objective of this research is to investigate thermal, power delivery network (PDN), and die-to-die signaling constraints in a proposed back-end-of-line (BEOL)-embedded polylithic integration architecture for dense 3D heterogeneous integration. Preliminary work includes two parts. First, a design parameter modeling study is performed to analyze thermal considerations for the proposed 3D integration architecture, with advanced cooling and heat spreading techniques, and to highlight the operation limits of each cooling technique. This study suggests that 3D ICs might require heat-sinking from multiple directions and, potentially, advanced backend heat spreading using higher thermal conductivity dielectric materials. Second, is an analysis to quantify the implications of the proposed 3D integration architecture and cooling techniques on the performance of emerging non-volatile memory devices in a 3D form factor for compute-in memory (CIM) applications, which have gained interest for energy-efficient computing. The goal here is to evaluate how the choice of 3D integration technique and cooling can impact the device retention of resistive random-access memory (RRAM) devices to estimate any change in image recognition accuracy of an RRAM-based CIM accelerator. The proposed research will focus on: PDN-thermal co-simulation for performance estimation of multi-level BEOL-embedded RRAM arrays with respect to CIM training and inference accuracy variation to benchmark 3D integration and cooling technologies, analyzing design trade-offs of backside power delivery for the proposed 3D integration scheme using buried power rails via distributed chip- and package-level PDN modeling, as well as developing die-to-die signaling models for the proposed backend-to-chiplet 3D polylithic bonds and benchmarking against other advanced integration architectures.
