*********************************
There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
*********************************
Atlanta, GA | Posted: November 3, 2020
Jackie Nemeth
School of Electrical and Computer Engineering
404-894-2906
Summary Sentence:
ECE Ph.D. students Brian Crafton, Samuel Spetalnick, and Gauthaman Murali and their faculty advisors won the Best Paper Award at this year's IFIP/IEEE International Conference on Very Large Scale Integration (VLSI SoC 2020).
Full Summary:
ECE Ph.D. students Brian Crafton, Samuel Spetalnick, and Gauthaman Murali and their faculty advisors won the Best Paper Award at this year's IFIP/IEEE International Conference on Very Large Scale Integration (VLSI SoC 2020).
Georgia Tech ECE Compute In-Memory Research Team Brian Crafton, Samuel Spetalnick, and Gauthaman Murali and their faculty advisors won the Best Paper Award at this year's IFIP/IEEE International Conference on Very Large Scale Integration (VLSI SoC 2020). The conference was held October 5-7 in a virtual format.
Crafton, Spetalnick, and Murali are all Ph.D. students in the Georgia Tech School of Electrical and Computer Engineering (ECE). Crafton and Spetalnick are advised by ECE Professor Arijit Raychowdhury, and Murali is advised by ECE Professor Sung-Kyu Lim. ECE Assistant Professor Tushar Krishna also joins Raychowdhury, Lim, and their students as co-authors on the paper.
The title of their work is "Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics." Compute In-Memory using emerging non-volatile memory technologies is an exciting technique that promises to minimize data transport, maximize memory throughput, and perform compute on the bitline of memory sub-arrays, thus accelerating machine learning and neuromorphic applications. However, this technique faces new challenges not faced in traditional CMOS memory fabrics. While the new memories provide high density and near-zero leakage power, they require significantly higher write energy than traditional CMOS-based memories. As a result, it is not practical to write the memories at high rates.
This work presents a novel technique to partition the data to be stored in the memory, by intelligently profiling the application in advance. The team demonstrates that for their target application, different operations in the workload require different time to execute on the same hardware. Using this insight, memory can be fairly allocated to maximize throughput and achieve significant speedup over prior work.
This research is funded by the Air Force Office of Scientific Research through the CEREBRAL MURI program and by SRC through the JUMP programs.
Photo caption (clockwise from upper left): Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, and Arijit Raychowdhury
