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Title: Design Methodology for Reliable and Energy Efficient Self-tuned On-chip Voltage Regulators
Committee:
Dr. Saibal Mukhopadhyay, ECE, Chair , Advisor
Dr. Abhijit Chatterjee, ECE
Dr. Sung Kyu Lim, ECE
Dr. Tushar Krishna, ECE
Dr. Hyesoon Kim, CoC
Abstract: The objective of the proposed research is to develop a robust design methodology for reliable and energy efficient self tuned on-chip voltage regulators, namely inductive integrated voltage regulators (IVR) and digital low dropout regulators (DLDO). The architectures and algorithms for a lightweight self tuning engines are explored for improved transient performance against process and passive variations. Reliability aspects of the different on-chip voltage regulators are further explored to study the effects of voltage stress on transient performance and efficiency. A prototype test-chip with an IVR and all-digital self tuning engines to enhance transient performance of the digital load, an AES encryption engine is developed. A specification to GDSII layout automated tool flow for on-chip voltage regulators is also developed to reduce the overall design time. On-chip voltage regulator architectures and corresponding time domain, frequency domain and efficiency models are explored for building the front end of the automated tool flow. A back end physical design flow and an design space pruning based optimization flow are also proposed for the automated tool flow to converge to designs optimized for specific targets. Additionally, a fully synthesized and flexible precision IVR architecture has also been developed to facilitate easy integration with the auto-generation tool flow and improve transient performance.
