Ph.D. Proposal Oral Exam - Siddharth Ravichandran

*********************************
There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
*********************************

Event Details
  • Date/Time:
    • Thursday April 23, 2020 - Friday April 24, 2020
      10:00 am - 11:59 am
  • Location: https://bluejeans.com/302683847
  • Phone:
  • URL:
  • Email:
  • Fee(s):
    N/A
  • Extras:
Contact
No contact information submitted.
Summaries

Summary Sentence: Design & Demonstration of 3D Glass Panel Embedded Package for Superior Bandwidth and Power Efficiency

Full Summary: No summary paragraph submitted.

Title:  Design & Demonstration of 3D Glass Panel Embedded Package for Superior Bandwidth and Power Efficiency

Committee: 

Dr. Tummala, Advisor   

Dr. Naeemi, Chair

Dr. Swaminathan

Dr. Peterson

Dr. Smet

Abstract:

The objective of the proposed research is to model, design and demonstrate a novel 3D embedded package technology for next-generation high-performance computing (HPC) systems. The proposed research focuses on the following objectives: (1) design a 3D package to achieve >1 Tbps bandwidth at <1 pJ/bit power-efficiency and (2) develop materials and processes to fabricate and demonstrate such a package. With the slowing down of Moore's law scaling, HPC systems today pursue heterogeneous integration of logic and memory chips on the package. Hence, the bandwidth and power-efficiency (measured as energy-per-bit) of chip-to-chip communication becomes the limiting factor in scaling system performance. These two key metrics are primarily driven by I/O count, interconnect length, wiring density and the choice of dielectric materials. Today, the technology options for package-level integration in HPC are either 2.5D/3D and chip-first/chip-last architectures. While 3D and chip-first technologies solve the interconnect length and I/O count challenges respectively, they are still fundamentally limited in scaling the driving factors for bandwidth and power-efficiency comprehensively. This research proposes a novel chip-first 3D packaging technology using glass-based panel embedding to simultaneously address I/O density and interconnect length while utilizing low-dk/df materials and low-loss polymer RDL technologies. Through modeling and characterization, the electrical design of such a system will be studied. A design-space exploration of key substrate parameters to assess the bandwidth and energy-per-bit potential of proposed structure will also be conducted and benchmarked against state-of-the-art technology options. The materials and processes will be studied and a stable fabrication process flow will be established to demonstrate such a 3D package in a panel-scalable, low-cost and thermo-mechanically reliable fashion.

Additional Information

In Campus Calendar
No
Groups

ECE Ph.D. Proposal Oral Exams

Invited Audience
Public
Categories
Other/Miscellaneous
Keywords
Phd proposal, graduate students
Status
  • Created By: Daniela Staiculescu
  • Workflow Status: Published
  • Created On: Apr 13, 2020 - 1:53pm
  • Last Updated: Apr 13, 2020 - 1:53pm