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Title: Design Methodology for Reliable and Energy Efficient Self-tuned On-chip Voltage Regulators
Committee:
Dr. Mukhopadhyay, Advisor
Dr. Lim, Chair
Dr. Chetterjee
Abstract:
The objective of the proposed research is to develop a robust design methodology for reliable and energy efficient self tuned on-chip voltage regulators, namely inductive integrated voltage regulators (IVR) and digital low dropout regulators (DLDO). The architectures and algorithms for a lightweight self tuning engines are explored for improved transient performance against process and passive variations. Reliability aspects of the different on-chip voltage regulators are further explored to study the effects of voltage stress on transient performance and efficiency. A prototype test-chip with an IVR and all-digital self tuning engines to enhance transient performance of the digital load, an AES encryption engine is developed. A specification to GDSII layout automated tool flow for on-chip voltage regulators (IVR and DLDO) is proposed to reduce the overall design time. On-chip voltage regulator architectures and corresponding time domain, frequency domain and efficiency models are explored for building the front end of the automated tool flow. A back end physical design flow and an design space pruning based optimization flow are also proposed for the automated tool flow to converge to designs optimized for specific targets. The research progress to date demonstrates improved transient performance of digital core with self tuning and higher resistance to voltage stress for IVR over DLDO. The remaining work will focus on acquiring and analyzing co-tuning and flexible precision measurements from a prototype testchip consisting of distributed system with an flexible precision IVR, DLDO and AES engine designed using the automated tool flow.
