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Title: Algorithm-hardware Co-design for Energy Efficient Machine Learning System
Committee:
Dr. Raychowdhury, Advisor
Dr. Bakir, Chair
Dr. Romberg
Abstract:
The objective of the proposed research is to design an energy efficient ML system for autonomous systems. An Algorithm-hardware co-design to reduce the number of training computations (and hence the energy and latency) by mapping the algorithm to a hierarchical memory sub-system. The underlying problem is drone autonomous navigation using deep reinforcement learning. Transfer learning was used to reduce the amount of resources required to train a deep neural network for the underlying problem by training the network on a set of rich and diverse meta environments, transferring the domain knowledge to test environments and training the last few fully connected layers only. STT-MRAM based embedded system was designed to complement the algorithmic approach by smartly mapping the weights to different memory technologies. The trainable part of the network was stored in a smaller but faster STT-MRAM with low write latency. The non-trainable part of the network was mapped onto off-chip DRAM. Since it won't be written into that often, the high write latency of DRAM will not be affecting the overall latency of the system. The algorithmic performance was measured in terms of Mean Safe Flight was similar to training the network end-to-end while reducing the latency & energy consumption by 79.4% and 83.45% respectively. The reduction in these parameters can make it possible for DRL training to be implemented on resource constrained edge nodes. Moreover, the approach was tested on a real environment using a low-cost drone and showed similar performance.
