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Title: Bayesian Learning and Optimization for High-Performance Microelectronic Packaging
Committee:
Dr. Swaminathan, Advisor
Dr. Raychowdhury, Chair
Dr. Mukhopadhyay
Abstract:
The objective of this research is to develop Bayesian learning based models and algorithms that enable accurate system-level optimization, design space exploration (DSE) and uncertainty quantification (UQ) of high-performance electronics used for high-speed signaling, power delivery and embedded passives in microelectronic packages.
