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Title: Design Methods For Self-Repairing Digital Logic
Committee:
Dr. David Keezer, ECE, Chair , Advisor
Dr. Abhijit Chatterjee, ECE
Dr. Linda Milor, ECE
Dr. Vijay Madisetti, ECE
Dr. Sundaresan Jayaraman, MSE
Abstract:
The objective of this research is to establish a systematic approach for the design of self-testable, self-correcting, self-repairing and self-healing digital systems. This self-test/self-repair methodology is accomplished autonomously, in a distributed fashion, so that it can scale as the size of the system grows. Modular redundancy and re-programmability are exploited to accomplish generic self-test and to enable self-repair in general, and self-healing in FPGAs. Error rates are measured throughout the design to distinguish between transient errors and permanent or semi-permanent logic faults. Original logic design is automatically transformed to this self-healing architecture via customizable software. Logic reconfiguration occurs automatically, replacing failing logic modules so that the system continues to operate error-free while partial dynamic reconfiguration is used to heal failing logic.
