MSE M.S. Defense – Abhishek Choudhury

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Event Details
  • Date/Time:
    • Monday November 8, 2010
      12:30 am - 2:30 am
  • Location: MaRC 351
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Summaries

Summary Sentence: MSE M.S. Defense – Abhishek Choudhury

Full Summary: Thesis Title: Chip-Last Embedded Low Temperature Interconnections With Chip-First DimensionsTime: 1:30 PM, Tuesday 8th November Location: MaRC 351

Thesis Title: Chip-Last Embedded Low Temperature Interconnections With Chip-First Dimensions

 

Abstract:

Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection.

This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.

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School of Materials Science and Engineering

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MSE_Interal_Event
Status
  • Created By: Bill Miller
  • Workflow Status: Published
  • Created On: Nov 5, 2010 - 6:52am
  • Last Updated: Oct 7, 2016 - 9:53pm