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There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
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Atlanta, GA | Posted: May 10, 2019
Jackie Nemeth
School of Electrical and Computer Engineering
404-894-2906
Summary Sentence:
Swamit Tannu, Poulami Das, and their Ph.D. advisor, Moinuddin Qureshi, won the Best Paper Award at the ACM Computing Frontiers Conference, held in Sardinia, Italy from April 30-May 2, 2019.
Full Summary:
Swamit Tannu, Poulami Das, and their Ph.D. advisor, Moinuddin Qureshi, won the Best Paper Award at the ACM Computing Frontiers Conference, held in Sardinia, Italy from April 30-May 2, 2019.
Swamit Tannu and Poulami Das (center and right), with graphic of the Josephson Junction Based SHA-256 Accelerators
Moin QureshiSwamit Tannu, Poulami Das, and their Ph.D. advisor, Moinuddin Qureshi, won the Best Paper Award at the ACM Computing Frontiers Conference, held in Sardinia, Italy from April 30-May 2, 2019.
Tannu and Das are students in the Georgia Tech School of Electrical and Computer Engineering (ECE) and are members of the Memory Systems Lab. The lab is led by Qureshi, who is an ECE professor.
The team received the award for their paper entitled “A Case for Superconducting Accelerators.” This study was done in collaboration with researchers from Microsoft, and the co-authors include Mike Lewis, Bob Krick, and Doug Carmean.
Superconducting circuits based on Josephson Junction (JJ) is an emerging technology that can provide devices which can be switched with pico-second latencies and consuming two orders of magnitude lower switching energy compared to CMOS. While JJ-based circuits can provide high operating frequency and energy-efficiency, this technology faces three critical challenges: lack of area-efficient technology for memory structures, reduced gate fanout compared to CMOS, and new failure modes of Flux-Traps that occur due to the operating environment.
The lack of dense memory technology restricts the use of superconducting technology in the near term to application domains that have high compute intensity but require a negligible amount of memory. This paper investigates the use of superconducting technology to build an accelerator for SHA-256 engines commonly used in Bitcoin mining applications.
This work shows that redesigning the accelerator to suit the unique constraints of superconducting technology, such as low fanout, can significantly improve energy efficiency. The paper also develops solutions to make the design tolerant of new fault modes and show how this fault-tolerant design can be leveraged to reduce the operating current, thereby increasing the overall energy-efficiency to 46X compared to the CMOS accelerator.
