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Title: Modeling and Simulation of FINFET SRAM Reliability Degraded by Various Wearout Mechanisms
Committee:
Dr. Milor, Advisor
Dr. Naeemi, Chair
Dr. Klein
Abstract:
The objective of this proposed research is to study FinFET SRAM reliability degradation due to various wearout mechanisms. Although small technology nodes bring various benefits such as higher device density, they also pose reliability challenges. Deeply scaled FinFETs have high sensitivity to time-zero variability and wearout mechanisms such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Gate-oxide Time Dependent Dielectric Breakdown (GTDDB), Random Telegraph Noise (RTN), and Electromigration (EM). The proposed work consists of two parts. The first part is about the modeling of FinFET SRAM degradation due to BTI, HCI, GTDDB, RTN, and EM. The second part is about the impact of front-end wearout mechanisms on FinFET SRAM cells’ soft error rate (SER). We study cache reliability degradation under different cache configurations such as associativity, cache line size, and cache size. A library based on Deep Neural Networks (DNNs) is proposed to speed up the process of obtaining FinFET SRAM cells’ degradation. Meanwhile, a simulation flow is built up to study how the front-end wearout mechanisms affect FinFET SRAM SER. The impact of cache configuration will be checked as well.
