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Title: ENERGY EFFICIENT PROCESSING IN MEMORY ARCHITECTURE FOR MACHINE LEARNING ACCELERATION
Committee:
Dr. Mukhopadhyay, Advisor
Dr. Khan, Chair
Dr. Raychowdhury
Abstract:
The objective of the proposed research is to explore the design of emerging Non-volatile Memory (NVM) based PIM architecture for DNN acceleration. At device level, I investigate both Resistive Random Access Memory (ReRAM) and Ferroelectric FET (FeFET) based memory cell; at array level, optimizations to read/write peripherals are applied to improve the computation efficiency; at micro-architecture level, I propose hierarchical network-on-chip (H-NoC) design for fast and efficient data transmission; last but not least, at application level, I explore various DNN models including CNN, LSTM, Object-detection network, etc. Incorporated with the circuit and architecture innovation, I also explore the network complexity reduction techniques and robust DNN design
