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Title: A holistic approach to the post-CMOS in/near-memory processing system design for machine learning and optimization
Committee:
Dr. Raychowdhury, Advisor
Dr. Khan, Chair
Dr. Swaminathan
Abstract:
The objective of this proposed research is to take a holistic approach to the post-CMOS in/near-memory processing system design for machine learning and optimizations. In the completed research section, we first address the current issues of Spin-Transfer Torque Magnetic Random Access Memory(STT-MRAM) and multi-bit ferroelectric FET in the device level. At the circuit level, the research shows how these issues shape the peripheral circuit of STT-MRAM and ferroelectric FET memory arrays. Lastly, at the system level, the research leads to the efficient memory architecture and system design that maximizes the benefits of STT-MRAM and ferroelectric FET while mitigating the current limitations of these devices. In the proposed research, we applies the in/near memory processing system design with STT-MRAM and ferroelectric FETs to various applications such as reinforcement learning with a drone, image classification with Deep Neural Network and least square minimization for image reconstruction. For the remaining part of this research, we will focus on near-memory processing system with STT-MRAM for reinforcement learning of a drone and evaluate the system to quantify how much benefits are expected in terms of latency, power and energy. From this project, we would like to show that near-memory processing system with non-volatile devices is a key enabler for a real-time learning systems with stringent power and energy constraints.
