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Atlanta, GA | Posted: February 7, 2018
Jackie Nemeth
School of Electrical and Computer Engineering
404-894-2906
Summary Sentence:
A paper by ECE Ph.D. student Reza Abbaspour is featured as one of the highlights for 2017 in the Journal of Micromechanics and Microengineering (JMM).
Full Summary:
A paper by ECE Ph.D. student Reza Abbaspour is featured as one of the highlights for 2017 in the Journal of Micromechanics and Microengineering (JMM).
Reza AbbaspourA paper by Reza Abbaspour is featured as one of the highlights for 2017 in the Journal of Micromechanics and Microengineering (JMM). Abbaspour is a Ph.D. student in the Georgia Tech School of Electrical and Computer Engineering (ECE).
The JMM 2017 Highlight Papers were chosen based on a number of criteria, including presentation of outstanding research, popularity with our online readership, and high praise from referees. Abbaspour’s paper, entitled “Fabrication and Electrical Characterization of Sub-Micron Diameter Through-Silicon Via for Heterogeneous Three-Dimensional Integrated Circuits,” was co-authored by Devin Brown, a senior research engineer with the Institute for Electronics and Nanotechnology, and ECE Professor Muhannad Bakir, Abbaspour’s Ph.D. advisor and the director of the Integrated 3D Systems Group.
Heterogeneous 3D integration of electronics is being explored as an innovative approach to high-performance and miniaturized computing systems, and it is enabled by vertically stacked silicon tiers interconnected using through-silicon-vias (TSVs). This approach represents a promising path to keep, and perhaps exceed, the pace of Moore’s law.
TSV is a fundamental enabler to 3D integration. The smaller the geometry of the TSVs, especially the diameter, the better the electrical signaling attributes and the lower the thermomechanical stresses. As such, there is a strong motivation for scaling TSV dimensions. Scaling TSVs, however, is challenging as the fabrication of smaller diameters using conventional processes faces limitations. Despite the relentless efforts to reduce the TSV footprint, virtually no results have been reported for high aspect-ratio copper-filled TSVs in bulk silicon with total diameter below one micron.
For the first time in this research paper, Abbaspour presents a sub-micron diameter TSV technology that allows for very fine-grain 3D integrated circuits (ICs). To address the challenges in scaling TSVs, novel fabrication techniques including scallop-free low roughness nano-Bosch process and direct copper electroplating on a titanium-nitride diffusion barrier layer have been developed as key enabling modules for this technology.
The demonstrated sub-micron TSVs feature an aspect-ratio of 16:1 with a 680 nm diameter copper core and a 920 nm overall diameter. To investigate the electrical performance of the scaled TSVs, the electrical resistance is measured and the copper resistivity extracted. In another effort by the group, TSVs with ~100 nm diameter were also demonstrated. Such aggressive TSV technologies open the door for very fine-grain 3D IC architectures not possible with conventional TSV and 3D IC technologies.
