*********************************
There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
*********************************
Title: Efficient Consistency in Emerging Systems and Architectures
Pranith Kumar
School of Computer Science
College of Computing
Georgia Institute of Technology
Data: Wednesday, January 24, 2018
Time: 11:30 AM to 1:00 PM EST
Location: KACB 1202
Committee
---------
Dr. Hyesoon Kim (Advisor), School of Computer Science, Georgia Institute of Technology
Dr. Milos Prvulovic, School of Computer Science, Georgia Institute of Technology
Dr. Santosh Pande, School of Computer Science, Georgia Institute of Technology
Abstract
--------
With the improvements in single core performance and processor clocks reaching
a plateau, diverse systems and architectures are being explored to keep pace
with Moore’s law. The different kinds of parallel processors being explored
are homogeneous, heterogeneous, and discrete offload-able systems. The most
common type processing systems is where the individual processors share
a single address space. One main challenge in parallel processing
architectures is ensuring memory consistency without sacrificing performance.
In this dissertation, we focus on reducing the overhead of memory consistency
in such parallel processing systems. Our first focus is on traditional
multi-core processors that implement the Release Consistency memory model
where we propose to use versions to reduce the consistency overhead. Next, we
work on near-data processing systems to identify bottlenecks and propose both
software and hardware techniques to reduce the consistency overhead. Finally,
we study cross-ISA virtual machines that when used for emulating strong memory
model architectures on weak architectures (x86 on ARM) and identify
overheads. We propose both software and hardware techniques to reduce this
overhead.