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Title: Performance Modeling and Optimization for On-chip Interconnects in Memory Arrays
Committee:
Dr. Azad Naeemi, ECE, Chair , Advisor
Dr. Muhannad Bakir, ECE
Dr. Jeffrey Davis, ECE
Dr. Oliver Brand, ECE
Dr. Yogendra Joshi, ME
Abstract:
In multi-core systems, the memory latency and bandwidth are among the key limitations. While interconnects have created major challenges for the integrated circuit technology in the past decades, there have been major changes in the nature and the severity of the challenges in recent years. Therefore, modeling and benchmarking the interconnect performance for memory chips is of utmost importance. The memory system design is facing many challenges. DRAM-based memory systems are stretched to meet the increasing demands on high memory bandwidth and large memory capacity that are required by multi-core processors. To address these challenges both technology and circuit solutions should be investigated. While this work focuses on a few memory technologies, the modeling approach presented here and the insights obtained regarding the limits and opportunities associated with interconnects apply to other emerging and conventional memory technologies.
