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Title: Model, Predict, and Mitigate Scalability Bottlenecks for Parallel Application on Many-core Processors
Ching-Kai Liang
Ph.D. Student
School of Computer Science
College of Computing
Georgia Institute of Technology
Date: Monday, November 27 2017
Time: 10:00AM - 12:00PM (EDT)
Location: Klaus 2100
Committee:
Dr. Milos Prvulovic (Advisor, School of Computer Science, Georgia Institute of Technology)
Dr. Hyesoon Kim (School of Computer Science, Georgia Institute of Technology)
Dr. Moinuddin Qureshi (School of Computer Science, Georgia Institute of Technology)
Dr. Sudhakar Yalamanchili (School of Electrical and Computer Engineering, Georgia Institute of Technology)
Dr. Christopher Hughes (Intel Labs, Intel)
Abstract:
In recent years, the number of processor cores on a single chip has increased rapidly, ranging from hundreds of cores in server processors to tens of cores on mobile processors.
The abundant number processing cores have led to application developers investing in parallizing applications in order to extract the maximum performance from many-core processors.
However, ensuring the continuous scaling of parallel applications is challenging on many-core processors, due to the complex relationship of available parallelism in application and the limited shared on-chip resources.
In this thesis, I will propose microarchitecture solutions to mitigate the scaling bottleneck as well as a new performance model to predict the how applications will scale on many-core processors.
First, I will propose MiSAR, a minimalistic synchronization accelerator that supports all three commonly used types of synchronization (locks, barriers, and condition variables),
and a novel overflow management unit that dynamically manages its (very) limited hardware synchronization resources.
Second, I will propose a new performance model that captures program characteristics of multi-threaded applications, allowing it to use few-threaded runs to predict performance of many-threaded runs.
