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Title: NeuroCube: Energy-efficient Programmable Digital Deep Learning Accelerator based on Processor in Memory Platform
Committee:
Dr. Saibal Mukhopadhyay, ECE, Chair , Advisor
Dr. Sudhakar Yalamanchili, ECE
Dr. Hyesoon Kim, CoC
Dr. Asif Khan, ECE
Dr. Sek Chai, SRI International
Abstract:
This thesis presents a programmable and scalable digital deep learning accelerator based on 3D high density memory integrated with logic tier for efficient deep learning computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE clusters access multiple memory channels (vaults) in parallel. The operating principle, referred to as the memory centric computing, embeds specialized state-machines within the vault controllers of HMC to drive data into the PE clusters. Moreover, applying approximate computing during the inference to save more power and the relationship between on-chip training conditions and approximate inference allows energy optimization for both inference and training. The proposed architecture is synthesized in 15nm FinFet technology and its area and power analysis is provided. The performance of the Neurocube is evaluated and illustrated through the mapping of different state of art Deep Neural Network and estimating the subsequent power and performance for both training and inference.
