Dwarakanath Wins IMAPS Best Paper Honors

*********************************
There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
*********************************

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Sidebar Content
No sidebar content submitted.
Summaries

Summary Sentence:

Georgia Tech Ph.D. student Shreya Dwarakanath won the Best of Track (Advanced Packaging) & Best Student Paper awards at the 49th International Symposium on Microelectronics (IMAPS), held October 10-13, 2016 in Pasadena, California.

Full Summary:

Georgia Tech Ph.D. student Shreya Dwarakanath won the Best of Track (Advanced Packaging) & Best Student Paper awards at the 49th International Symposium on Microelectronics (IMAPS), held October 10-13, 2016 in Pasadena, California.

Media
  • Shreya Dwarakanath Shreya Dwarakanath
    (image/jpeg)

Shreya Dwarakanath won the Best of Track (Advanced Packaging) & Best Student Paper awards at the 49th International Symposium on Microelectronics (IMAPS), held October 10-13, 2016 in Pasadena, California.

Dwarakanath received the award for her paper entitled “Electrodeposited copper-graphite composites for low-CTE integrated thermal structures.” As an award winner, she is invited to attend the IMAPS 2017 Symposium in Raleigh, North Carolina, where she will receive her award.  Dwarakanath is a Ph.D. student in the Georgia Tech School of Materials Science and Engineering, and she is advised Professor Rao R. Tummala and mentored by Senior Research Engineer Raj M. Pulugurtha, both of Tech’s School of Electrical and Computer Engineering.

Emerging high-power and high-temperature electronic modules require thick copper (Cu) structures for power-supply, thermal vias, heat-spreaders, and also as carriers or lead-frames for high-power packages. Such structures should coexist with glass and other low-CTE substrates to meet high-temperature performance, dimensional stability, and superior device interconnection reliability with low stresses and warpage. The primary challenge with these packages arises from the coefficient of thermal expansion (CTE) mismatch between the conductors and the substrates.

In order to address this challenge, Cu-graphite composites with glass-matched CTE were explored through analytical modeling of properties such as CTE, Young’s modulus and thermal conductivity, FEM predictions of glass warpage and stresses, process development to deposit copper-graphite composite films with high graphite loading, and warpage measurements using shadow-moiré. Results indicate that Cu-graphite composites can mitigate the warpage and stress issues in high-temperature and high-power packages.

Related Links

Additional Information

Groups

School of Electrical and Computer Engineering

Categories
Student Research, Research, Chemistry and Chemical Engineering, Engineering, Nanotechnology and Nanoscience, Physics and Physical Sciences
Related Core Research Areas
Electronics and Nanotechnology, Materials
Newsroom Topics
No newsroom topics were selected.
Keywords
Shreya Dwarakanath, Rao Tummala, Raj M. Pulugurtha, International Symposium on Microelectronics, coefficient of thermal expansion, thermal structures, copper, electronic modules, Georgia Tech, School of Electrical and Computer Engineering, School of Material Science and Engineering
Status
  • Created By: Jackie Nemeth
  • Workflow Status: Published
  • Created On: Jul 20, 2017 - 2:05pm
  • Last Updated: Jul 20, 2017 - 2:08pm