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Title: Electrical Modeling, Design, Demonstration and Thermal Reliability of Sub 25um TPVs at Fine Pitch in Ultra-thin 3D Glass Interposers for RF Applications
Committee:
Dr. Rao Tummala, ECE, Advisor
Dr. Manos Tentzeris, ECE
Dr. Venkatesh Sundaram, PRC
Dr. Raj Pulugurtha, PRC
Abstract:
System scaling by 3D packaging is now considered a critical technology enabler for continued increases in system data bandwidth, at lowest power and cost. Ultra-high chip-to-chip interconnect bandwidth is required for a number of new applications including 5G communications, V2V (vehicle-to-vehicle) and V2N (vehicle-to-network) connectivity. The best approach to increase bandwidth between multiple ICs is to interconnect them at the shortest path length possible. Although direct chip stacking with through silicon vias (TSV) was developed as the primary approach for 3D integration, thermal and cost problems have limited their applicability . Georgia Tech previously proposed and demonstrated 3D interposers as a superior alternative to achieve 3D-IC like interconnect lengths at much lower cost and without the thermal problems. Glass is the best material for 3D interposer packages due to its superior dimensional stability and flatness compared to organic laminates, and large panel scalability and lower loss compared to silicon. The single biggest barrier to 3D glass interposers is the formation of through package vias (TPVs) in ultra-thin glass substrates at the same pitch and height as TSVs. Although initial research into formation methods and metallization processes for ultra-thin glass TPVs was reported by Georgia Tech researchers, this dissertation represents the first complete study on the electrical modeling of TPVs at 50 µm pitch in 50 µm ultra-thin glass up to 30 GHz. Two major applications are expected to have major impact from this research, namely, (a) logic-memory high density interconnections for digital bandwidth, and (b) mm-wave IC to antenna low loss interconnections for small form factor 5G modules.
