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Title: Scalable Algorithms and Design for Debug Hardware for Test, Validation and Security of Mixed Signal / RF Circuits and Systems
Committee:
Dr. Abhijit Chatterjee, ECE, Chair , Advisor
Dr. Jennifer Hasler, ECE
Dr. Saibal Mukhopadhyay, ECE
Dr. Arijit Raychowdhury, ECE
Dr. Adit Singh, Auburn University
Abstract:
With the advent of SOCs and SOPs, more functionalities are integrated into an IC or package. Higher level of integration has made testing, validation of ICs more challenging due to lack of observability of internal circuit nodes. This calls for new embedded Design for Test (DFT) circuit design and test methodology development. This work is geared towards solving the analog/RF testing problem mentioned above by crafting intelligent stimulus to excite the non-idealities of the circuit, along with machine learning algorithms to learn the behavior of the system. Though the manufacturing cost of a transistor is decreasing over the technology generations, test cost per transistor is remaining constant or decreasing at a lower rate. So there will be a time when test cost per transistor will be more than the actual manufacturing cost of a transistor. Every newer technology advancement entails newer test methodologies for keeping the test cost at a certain bound. ATE cost for mixed-signal and RF ICs are higher than that of digital ICs. There is a need in industry for low cost efficient testing, tuning and validation methodologies for mixed-signal and RF circuits and systems. In this thesis we have addressed the following validation problems:
i) Manufacturing testing (Process Adaptive RF Transceiver Testing)
ii) Post manufacture tuning (Learning Assisted Parallel Testing and Tuning of Massively Beam-forming MIMO systems)
iii) Pre and post silicon verification (Built In State Consistency Checking for Mixed-Signal/RF Verification)
