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Title: Integrated Three-axis Accelerometers with Nanometer Scale Capacitive Gaps and Signal Conditioning Interface IC
Committee:
Dr. Farrokh Ayazi, ECE, Chair , Advisor
Dr. Oliver Brand, ECE, Co-Advisor
Dr. Maysam Ghovanloo, ECE
Dr. Omer Inan, ECE
Dr. Gabriel Rincon-Mora, ECE
Dr. Peter Hesketh, ME
Abstract:
This dissertation investigates on the design and characterization of three-axis MEMS accelerometers with nano-sensing-gap, interfaced with low-noise signal conditioning readout IC. As the technology continuously advances, there is a growing demand for wide-bandwidth, precision accelerometer, which is hard to implement using existing methodology. To meet such demands, high-aspect ratio (>100:1) deep sub-micron sensing gap (< 300nm) was employed. Doing so boost the amount of electro-mechanical coupling so that the operational bandwidth of sensor can be extended without sacrificing its noise performance. Furthermore, the use of nano-gap increases the air-damping so that the quasi-static accelerometer can be operated at low-pressure level without instability issues. This eases the sensor fusion by integrating acceleration sensor with different resonant devices under common wafer-level vacuum-packaged environment, enabling the single-chip inertial-measurement-unit (IMU) in a reduced form-factor and fabrication cost. A novel sloped electrode was also proposed to create a shock-stop without additional fabrication steps, and hence provide device robustness against extreme shock environment (>1,000 g). The displacement of the transducer is converted to an electrical signal using switched-capacitor (SC) interface IC, where dynamic noise reduction method was used to suppress low-frequency noise. Furthermore, on-chip calibration block that employs time-averaged charge-tuning scheme suppresses any non-ideal capacitive mismatch of the MEMS element so that improved dynamic range as well as sensitivity can be achieved. The overall characterization results show that the reported accelerometer can achieve operational bandwidth higher than 10 kHz, while maintaining noise level close to 100 μg/√Hz, which is not possible using commercial accelerometers. Presented design methodology can be a promising candidate to meet demands from newly-emerging technologies.
