*********************************
There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
*********************************
Title: Architecting High-performance, Efficient and Scalable Heterogeneous Memory System with 3D-DRAM
Committee:
Dr. Moinuddin Qureshi, ECE, Chair , Advisor
Dr. Sudhakar Yalamanchili
Dr. Hyesoon Kim, CoC
Dr. Tushar Krishna, ECE
Dr. Aamer Jaleel, NVIDIA
Abstract:
In past decades, processors have incorporated more and more compute power and demanded higher memory bandwidth. As recent packaging advancement enables high-bandwidth 3D-stacked dynamic random access memory (DRAM), 3D-DRAM and high-capacity memory form a heterogeneous memory system. However, managing such systems with conventional management techniques that are developed for small on-chip caches or non-uniform-memory-access systems delivers sub-optimal performance. This dissertation investigates the problem of architecting a high-performance heterogeneous memory system and proposes simple architectural innovations that address the challenge of the hardware management of 3D-DRAM and the resource utilization and the scalability of the system.
