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Title: Performance Modeling and Optimization for On-chip Interconnects in Memory Arrays
Committee:
Dr. Naeemi, Advisor
Dr. Bakir, Chair
Dr. Davis
Abstract:
The objective of the proposed research is to do the performance modeling and optimization for different memory technologies for future technology generations with a focus on on-chip interconnects. While interconnects have created major challenges for the integrated circuit technology in the past decades, there have been major changes in the nature and the severity of the challenges in recent years. In the past, only the long global interconnects imposed limits on the chip clock frequency since the delay of local interconnects scaled with technology. However, the increase in the copper resistivity due to size effects such as surface/grain boundary scattering, and line edge roughness have led to a significant increase in local interconnect delay causing it to become a challenge, too. There have been many publications on the interconnect scaling issues in logic chips. However, there has been no comprehensive study on the performance and scalability of interconnects in memory arrays.
