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Title: Design Methodologies for Scalable and Reliable Computer Systems
Committee:
Dr. Milor, Advisor
Dr. Swaminathan, Chair
Dr. Chatterjee
Abstract:
The objective of the proposed research is to develop design methodologies that enable scalable and reliable memory systems. To achieve low cost per bit, memory technology continues to scale down to small feature sizes so that core arrays of memory have become extremely dense. Because of such high densities, cells are more vulnerable to reliable issues. Scaling of supply voltage, not proportional to scaling of feature size, raises further reliability concerns than previous fabrication process technology generations, which increases electrical field in dielectric and in silicon. The increased electrical field in dielectric leads to more wearout failures in memory. The goal of this proposal is to propose circuit- and system-level support for continuous memory scaling and develop a methodology that tests and estimates reliability of a circuit and a system with accelerated life test at circuit and system level.
