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Title: Self-adjusting Pipeline Design and Tuning Methods for Timing Variation Tolerance
Committee:
Dr. Abhijit Chatterjee, ECE, Chair , Advisor
Dr. Sudhakar Yalamanchili, ECE
Dr. Saibal Mukhopadhyay, ECE
Dr. Arijit Raychowdhury, ECE
Dr. Adit Singh, Auburn
Abstract:
One of the challenges faced today in the design of microprocessors is to obtain power, performance scalability and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay behavior of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties in microprocessor pipelines, safety margins are incorporated by operating the design at a higher voltage or lower frequency. Incorporating one time worst-case guard-bands is a temporary solution to an increasing timing variation problem at lower technology nodes due to two reasons (1) How much guard-bands will be enough to guarantee reliable operation under delay variations is not known, which may result in difficult-to-model or difficult-to-detect speed/timing related bugs to escape into the field, resulting in a system failure during application execution (2) The degree/amount of guard-bands to be incorporated to ensure reliability continues to increase resulting in significant power and performance inefficiency. The first part of this thesis describes a low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system. The second part of this thesis details the design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins. Quantitative and qualitative analysis demonstrate great potential for energy, throughput benefits at lower technology nodes.
