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Title: Scalable Algorithms and Design for Debug Hardware for Test, Validation and Security of Mixed Signal / RF Circuits and Systems
Committee:
Dr. Chatterjee, Advisor
Dr. Hasler, Chair
Dr. Mukhopadhyay
Abstract: The objective of the proposed research is to develop DFX algorithms and infrastructures for test, validation and security of RF/Mixed-Signal systems. With the advent of SOCs and SOPs, more functionality is being integrated into Systems-on-Chips (SoCs) and Systems-on-Packages (SoPs) at an aggressive pace by industry. Higher levels of integration have made testing and post-silicon validation of such systems very difficult due to lack of observability and controllability of internal circuit nodes. A related problem stemming from silicon manufacture by third party vendors is that of ensuring that the hardware designs have not been maliciously altered for the purpose of sabotage. We address the testing and validation problems for mixed-signal systems by use of intelligent test stimulus generation algorithms and on-chip as well as off-chip test response analysis infrastructure (hardware as well as software). The test methodology is capable of supporting rapid built-in tuning and calibration of mixed-signal systems as well. For detecting malicious hardware Trojans, specialized stimulus for digital and analog circuits is used with the objective of ensuring that the observed response is maximally sensitive to changes in electrical loading of internal circuit nodes due to the presence of Trojan hardware. It is seen that the test generation methodology studied earlier can be seamlessly applied for the purpose of designing analog physically unclonable functions for SoC authentication.
