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There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
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Sudhakar Yalamanchili
Georgia Institute of Technology
School of Electrical and Computer Engineering
For more information please contact Dr. Rich Vuduc at richie@cc.gatech.edu
Title:
Ocelot: An Infrastructure for Analysis and Workload Characterization of Accelerated Applications
Abstract:
The rapid emergence of GPGPU architectures and their integration into commodity systems has produced significant productivity and software development challenges. These challenges are accompanied by a dearth of productivity tools for application development and analysis. In particular, the migration of existing compute intensive applications to these new CPU-GPGPU platforms suffers from a lack of productivity tools that can provide insights into candidate code segments that can benefit from acceleration, an assessment of most appropriate target platform, debugging, and support for subsequent performance tuning.
This talk will describe the Ocelot infrastructure being developed to address this lack of productivity tools for accelerated computing. Ocelot is emulation, compilation, and workload characterization environment targeted for CPUs accelerated with NVIDIA GPUs. The talk will describe our vision for Ocelot and progress date. Using Ocelot, CUDA kernels are transparently executed on a target GPU device, emulated in software in the host, or translated to be executed natively on a multithreaded multicore host (e.g., x86). Ocelot is being integrated with the Harmony runtime being developed in our group to enable performance portability and binary portability across platform sizes, e.g., different numbers and types of NVIDIA accelerators. Examples are presented of the analysis of emerging benchmarks in the research community such as Parboil, Rodinia, and the CUDA SDK.
Bio:
Sudhakar Yalamanchili earned his PhD degree in Electrical and Computer Engineering in 1984 from the University of Texas at Austin after which he joined Honeywell’s Systems and Research Center in Minneapolis where he worked as a Senior, and then Principal Research Scientist from 1984 to 1989. In both capacities, he served as the Principal Investigator for projects in the design and analysis of multiprocessor architectures for embedded applications. While at Honeywell, Dr. Yalamanchili also served as an Adjunct Faculty and taught in the Department of Electrical Engineering at the University of Minnesota. He joined the ECE faculty at Georgia Tech in 1989 where he is now a Joseph M. Pettit Professor of Computer Engineering. He is the author of VHDL Starters Guide, 2nd edition, Prentice Hall 2004, VHDL: From Simulation to Synthesis, Prentice Hall, 2000, and co-author with J. Duato and L. Ni, of Interconnection Networks: An Engineering Approach, Morgan Kaufman, 2003.
Dr. Yalamanchili is a Senior Member of the IEEE. He has served as a Distinguished Visitor of the IEEE, and on the editorial boards of the IEEE Transactions on Parallel and Distributed Processing and IEEE Transactions on Computers. He contributes professionally through service on conference and workshop program committees in the area of high performance computing, computer architecture, and interconnection networks.
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You are cordially invited to attend a reception in the lounge next to Klaus 1324 before the seminar to chat informally with faculty and students. PIZZA will be provided.
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