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Title: Exploiting On-Chip Memory Concurrency in 3D Many-Core Architectures
Committee:
Dr. Yalamanchili, Advisor
Dr. Qureshi, Chair
Dr. Mukhopadhyay
Abstract:
The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases in memory-level concurrency. This in turn affects the design of the multi-core interconnect and organization of the memory hierarchy. The work addresses the need for re-optimization in the presence of this increase in concurrency in the memory system. First, we observe that 2D network latency and inefficient parallelism management in the current 3D designs are the main bottlenecks to fully exploit the potentials of 3D. To that end, we propose an extremely low-latency, low-power, high-radix router and present its various versions for different network typologies and configurations. We also explore optimizations and techniques to reduce the traffic in the network. Second, we propose a reorganization of the memory hierarchy and associated optimizations. Third, we use simple address space translations to regulate locality, bandwidth and energy trade-offs in highly concurrent 3D memory systems, and hence manage them efficiently to improve overall system power and performance. Related techniques that developed include concurrency management of highly-parallel DRAM refresh, bank-parallelism aware cache replacement and coordinated management of banked LLC and DRAM.
