*********************************
There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
*********************************
Ph.D. Dissertation Defense Announcement
---------------------------------------------------------------
Title: Algorithmic Techniques for the Micron Automata Processor
Indranil Roy
School of Computational Science and Engineering College of Computing Georgia Institute of Technology
Date: Friday, April 24, 2015
Time: 3:30pm - 5:30pm EST
Location: KACB 1315
Committee:
-----------------
Prof. Srinivas Aluru (Advisor,
School of Computational Science and Engineering, Georgia Tech) Prof. Alberto Apostolico
(School of Interactive Computing;
School of Computational Science and Engineering, Georgia Tech) Prof. David A. Bader
(School of Computational Science and Engineering, Georgia Tech) Prof. Richard Vuduc
(School of Computational Science and Engineering, Georgia Tech) Prof. Sudhakar Yalamanchili
(School of Electrical and Computer and Engineering, Georgia Tech)
Abstract:
This research is the first in-depth study in the use of the Micron Automata Processor, a novel re-configurable streaming co-processor which is purpose-built to execute thousands of Non-deterministic Finite Automata (NFA) in parallel. By design, this processor is well-suited to accelerate applications which need to find all occurrences of thousands of complex string-patterns in the input data. We have validated this by implementing two such applications, one from network security and the other from bioinformatics, both of which are significantly faster than their state-of-art counterparts. Our research has also widened the scope of the applications which can be accelerated through this processor by finding ways to quickly program any generic graph into it and then search for hard to find features like maximal-cliques and Hamiltonian paths. These applications and algorithms have yielded valuable design-inputs for next generation of the chip which is currently in design phase. We hope that this work paves the way to the early adoption of this upcoming architecture and to efficient solution of some of the currently computationally challenging problems.
