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There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
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Speaker: Victoria Caparros
Host: Richard Vuduc
Joint CompArch/CSE seminar
Extending the Roofline Model: Bottleneck Analysis with Microarchitectural Constraints by Victoria Caparros, ETH Zürich
Friday October 24, 2014
2-3 pm, Van Leer C241
Abstract:
Software, even if carefully optimized, rarely reaches the peak performance of a processor. Understanding which hardware resource is the bottleneck is difficult but important as it can help with both further optimizing the code or deciding which hardware component to upgrade for higher performance. If the bottleneck is the memory bandwidth, the roofline model provides a simple but instructive analysis and visualization. In this paper, we take the roofline analysis further by including additional performance-relevant hardware features such as latency, throughput, capacity information for a multilevel cache hierarchy and out-of-order execution buffers. Two key ideas underlie our analysis. First, we estimate performance based on a scheduling of the computation DAG on a high-level model of a microarchitecture and extract data including utilization of resources and overlaps from a cycle-by-cycle analysis of the schedule. Second, we show how to use this data to create only one plot with multiple rooflines that visualize performance bottlenecks. We validate our model against performance data obtained from a real system, and then apply our bottleneck analysis to a number of floating-point kernels to identify and interpret bottlenecks.
Bio:
Victoria Caparros is a Ph.D. student at ETH Zürich under the supervision of Prof. Markus Püschel. Her research interests are performance modeling and evaluation of computing systems. She is interested in building models and tools to analyze performance that are between traditional high-level analytical models and detailed microarchitectural simulation. With this purpose, she developed an LLVM-based tool that allows analyzing the performance of kernels on different microarchitectural models. Such a tool can be used to guide the code optimization process, diagnose performance bottlenecks, predict performance scalability, or make educated guesses on which hardware features match application properties.
Prior to joining ETH, she did her Master Thesis and worked as a predoctoral researcher at IBM Research Zürich.
