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Atlanta, GA | Posted: August 12, 2014
Jackie Nemeth
School of Electrical and Computer Engineering
404-894-2906
Summary Sentence:
ECE's Amit Ranjan Trivedi is one of three recipients of the 2014 IEEE Electron Devices Society (EDS) Ph.D. Fellowship and is the sole winner from the United States.
Full Summary:
ECE's Amit Ranjan Trivedi is one of three recipients of the 2014 IEEE Electron Devices Society (EDS) Ph.D. Fellowship and is the sole winner from the United States.
Amit TrivediAmit Ranjan Trivedi is one of three recipients of the 2014 IEEE Electron Devices Society (EDS) Ph.D. Fellowship and is the sole winner from the United States. This award will be presented to Trivedi at the annual IEEE EDS Meeting, to be held December 15-17 in San Francisco.
Trivedi is the second student from Georgia Tech to win this fellowship over the last 13 years. He is a member of the Gigascale Reliable Energy Efficient Nanosystem Lab, which is directed by his Ph.D. advisor Saibal Mukhopadhyay. Both Trivedi and Mukhopadhyay are affiliated with the School of Electrical and Computer Engineering.
In his thesis, Trivedi studies the applications of emerging technologies that will enable ultra-low power computing. He is specifically looking at the unique and rich characteristics of several emerging technologies, such as Tunnel FET, that can play a prominent role in alternate computing architectures such as those inspired by neuromorphic computing.
An ultra-low power Tunnel FET-based neuromorphic design can be process variation resilient and energy efficient, while exploiting parallelism and benefiting from mass transistor density at nanometer scaled technologies to deliver high performance. Ultra-low power neuromorphic designs can be used to solve complex tasks such as recognition and classification in remotely and ubiquitously deployed electronics, and provides outstanding opportunities for upcoming computing platforms such as the internet-of-things.
Trivedi also investigates other state-of-the-art technologies such as FinFET and 3D integration in aspects of arising variability. He has also designed and measured a test-chip to reduce power dissipation in CMOS designs while tolerating process and temperature variability.
