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Atlanta, GA | Posted: July 28, 2014
Jackie Nemeth
School of Electrical and Computer Engineering
404-894-2906
Summary Sentence:
ECE Ph.D. student Tom Sarvey won the Best Poster Award at the 2014 IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), held May 27-30 in Orlando, Florida.
Full Summary:
ECE Ph.D. student Tom Sarvey won the Best Poster Award at the 2014 IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), held May 27-30 in Orlando, Florida.
Tom SarveyTom Sarvey, a Ph.D. student in the School of Electrical and Computer Engineering (ECE) at Georgia Tech, won the Best Poster Award at the 2014 IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm). The conference was held May 27-30 in Orlando, Florida.
The title of Sarvey's award-winning paper is "Thermal and Electrical Effects of Staggered Micropin-Fin Dimensions for Cooling of 3D Microsystems." His coauthors are his Ph.D. advisor and ECE Associate Professor Muhannad Bakir and his fellow lab mates and ECE Ph.D. students Yang Zhang, Yue Zhang, and Hanju Oh in the Integrated 3D Systems Group.
As integrated circuit scaling hits major technical and economic limitations, 3D integration has become one of the most promising methods of continuing this trend in increasing system performance. However, 3D stacking of chips only exacerbates heat dissipation, which is already a major performance barrier.
A promising solution to the 3D thermal problem is microfluidic cooling, where a liquid coolant is pumped through micro-scale cooling structures built directly into the silicon. The high heat transfer coefficients of these small structures, as well as their close proximity to the heat generating circuitry, make them superior to traditional cooling systems.
Although often ignored in the thermal community, electrical signals must also be routed through these microfluidic heat sinks. To address this issue, Bakir's group has built copper through-silicon vias (TSVs) in micropin-fin heat sinks. In this work, the electrical impacts of micropin-fin dimensions were analyzed in terms of inter-tier signaling delay. Several electrically inspired micropin-fin heat sinks were fabricated and tested. The extracted thermal resistances were then used to simulate the temperature of an interposer-cooled memory on processor (Intel Core i7) stack, yielding up to a 23.3 K drop in maximum processor temperature.
