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There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
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Atlanta, GA | Posted: July 23, 2014
Jackie Nemeth
School of Electrical and Computer Engineering
404-894-2906
Summary Sentence:
ECE Professors Sudhakar Yalamanchili and Saibal Mukhopadhyay and their recently graduated students, Subho Chatterjee and Mitchelle Rasquinha, received the 2014 IEEE Circuits and Systems Society Very Large Scale Integrated Systems Best Paper Award.
Full Summary:
ECE Professors Sudhakar Yalamanchili and Saibal Mukhopadhyay and their recently graduated students, Subho Chatterjee and Mitchelle Rasquinha, received the 2014 IEEE Circuits and Systems Society Very Large Scale Integrated Systems Best Paper Award.
IEEE VLSI Systems Best Paper Award winnersProfessors Sudhakar Yalamanchili and Saibal Mukhopadhyay and their recently graduated students, Subho Chatterjee and Mitchelle Rasquinha, received the 2014 IEEE Circuits and Systems Society Very Large Scale Integrated Systems Best Paper Award.
The team, all from the Georgia Tech School of Electrical and Computer Engineering, was presented with this honor on June 3 at the IEEE International Symposium on Circuits and Systems, held in Melbourne, Australia. Their award-winning paper is entitled “A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective,” and the work presented in this paper was supported by the National Science Foundation and Intel Corporation.
Spin-Torque-Transfer RAM (STTRAM) is an emerging non-volatile memory technology that can retain information with practically no energy loss; it has the potential to dramatically transform the energy landscape of future computing systems. However, to realize the energy-efficiency potential of STTRAM in designing energy-efficient processing architectures, the interactions between the unique device physics of STTRAM, processor architecture, and the applications must be understood. This paper presents a modeling and analysis framework that can be used to understand these interactions, particularly from an energy perspective. The framework uses this understanding to explore the circuit-architecture design space of this emerging memory technology for the design of energy-efficient memory hierarchies in modern processors.
This paper has served as a timely bridge between the physics of Magnetic Tunneling Junction (MTJ) devices, circuit techniques for STTRAM cell design, and microarchitectural considerations for the use of STTRAM technology in caches. The energy analysis and observations from this paper have also made important contributions in understanding the potential role of STTRAM in computing.
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Pictured in the photos from left to right are ECE Professor Sudhakar Yalamanchili, Subho Chatterjee, Circuits and Systems Society (CAS) President-Elect Franco Maloberti, and Thanos Stouraitis who is the CAS Past President.
