*********************************
There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
*********************************
In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. This uses uniform repeaters (UR). In this talk, two novel surfing techniques, one using uniform repeaters (UR) and another using non-uniform repeaters (NUR), are presented for differential wave-pipelined serial interconnects. The method of logical effort is also proposed for the design of both UR and NUR. To evaluate the efficiency of these techniques, 40 mm metal 4 interconnects using the proposed surfing techniques are implemented along with transmitter, receiver, and delay locked loop(DLL) in UMC 180nm technology and their performances are studied through post-layout simulations. From this study, it is observed that the differential surfing technique using UR and NUR achieve 3.0 times and 4.15 times higher data rates, respectively, compared to the single ended scheme whose maximum data rate is 1.33 GB/s. The proposed scheme has the ability to receive the correct data even with stuck-at-faults in the complementary line.
Speaker Bio:
B. Venkataramani received the B.E. (Honours) degree in electronics and communication engineering from Regional Engineering College, Tiruchirappalli, India and the M.Tech. and Ph.D. degrees in electrical engineering from Indian Institute of Technology, Kanpur, India, respectively. He worked as deputy engineer in Bharath Electronics, Ltd., Bangalore, India, and as a research engineer in the Indian Institute of Technology, each for approximately three years. Since 1987, he has been with the faculty of the National Institute of Technology, Trichy (formerly known as Regional Engineering College, Trichy). Currently he is a professor in the Electronics and Communication Department and dean (Research and Consultancy). He has a patent and has authored two books and numerous papers in journals and international conferences. He has guided eight Ph.D. theses. He has executed R&D projects worth $0.6 million. His current research interests include field-programmable gate array (FPGA), system on a single chip (SOC)-based system design, analog VLSI design, and performance analysis of high-speed interconnects.
