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There is now a CONTENT FREEZE for Mercury while we switch to a new platform. It began on Friday, March 10 at 6pm and will end on Wednesday, March 15 at noon. No new content can be created during this time, but all material in the system as of the beginning of the freeze will be migrated to the new platform, including users and groups. Functionally the new site is identical to the old one. webteam@gatech.edu
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Atlanta, GA | Posted: June 7, 2012
Jackie Nemeth
School of Electrical and Computer Engineering
404-894-2906
Summary Sentence:
ECE Ph.D. student Chenyun Pan wins Best Student Paper Award at the International Conference on IC Design and Technology.
Full Summary:
ECE Ph.D. student Chenyun Pan wins Best Student Paper Award at the International Conference on IC Design and Technology.
chenyun panChenyun Pan won the Best Student Paper Award at the International Conference on IC Design and Technology. Mr. Pan is a Ph.D. student in the School of Electrical and Computer Engineering (ECE) at Georgia Tech.
The conference, which was sponsored by IEEE and the Japan Society of Applied Physics, was held in Austin, Tex. from May 30-June 1. Mr. Pan was honored for his paper entitled "System-Level Optimization and Benchmarking of Graphene pn Junction Logic System Based on Empirical CPI Model," which he coauthored with his Ph.D. advisor, Azad Naeemi, who is an assistant professor in ECE.
Mr. Pan's paper presents an empirical cycle-per-instruction (CPI) model for microprocessors to quantify the throughput of a chip integrating emerging transistor and interconnect technologies without the detailed design of a full microprocessor. This CPI model along with a host of generic models for critical path delay, power dissipation, and multilevel interconnect networks provide a powerful methodology for device/architecture co-optimization. Graphene pn junction devices are taken as a case-study for co-optimizing device level parameters (e.g., device geometry and dimensions) and system-level parameters (e.g., number and complexity of cores). It is demonstrated that optimal system-level parameters strongly depend on the choice of technology, and technology/system co-optimization is essential for benchmarking the potential performance of emerging post-CMOS switches.
